The present invention relates to a non-volatile memory system for data storage and retrieval, where the system comprises a memory having memory locations which can be written to individually but which can only be erased in blocks of locations, and a controller for controlling access to these memory locations; the present invention also relates to a non-volatile memory for use in such a non-volatile memory system and to a controller for controlling the non-volatile memory. In particular, the invention relates to FLASH memory systems having defective memory locations and controllers for FLASH memories.
FLASH EPROM (erasable programmable read only memory) devices are commonly used in the electronics industry for non-volatile data storage. FLASH memory devices are architecturally configured to have locations which may be written to individually but may only be erased in groups called erasable blocks. This architectural configuration arises because groups of transistors in FLASH memory are linked by a common erase line. Thus, the size of an erasable block (the number of storage locations) is determined by the architecture of the device, which is established at the design and manufacturing stage, and cannot be altered by the user.
One application of data storage is storing data structures generated by, for example, a Personal Computer (PC). A problem arises if FLASH memory having defective memory locations is used to store data structures because these defective memory locations cannot be used reliably for data storage.
One solution to this problem of having defective locations in a memory is for the FLASH controller to avoid using any erasable blocks containing a defective location. However, if erasable blocks containing defective locations are never used (marked as unusable by the controller) then there may be a great waste of usable memory storage space (depending on the size of the erasable blocks and the number of usable memory locations therein) leading to a low memory harvest (a low ratio of usable memory locations to total memory locations).
It is an object of the present invention to provide a non-volatile memory system which obviates or mitigates the above disadvantage.
It is an object of the present invention to provide a non-volatile memory system including a memory having locations that are not usable for data storage, but where the memory can be used for efficient storage and retrieval of data structures.
According to a first aspect of the present invention there is provided a memory system for connection to a host, the system comprising:
a non-volatile memory having memory locations,
and a controller for writing data structures to and reading data structures from the memory, the system being architecturally configured so that the locations can be written to individually but can only be erased in blocks of locations;
the improvement being that the controller forms at least one erasable unit, where each erasable unit comprises at least one erasable block, and the controller subdivides each erasable unit into groups of locations (where each group is herein called a cell) and the controller writes data structures to and reads data structures from each cell on a per cell basis.
By virtue of the present invention, the memory is re-configured into cells so that the controller may avoid using an individual cell containing a defect, rather than having to avoid using an erasable block containing a defect. This has the effect of increasing the memory harvest.
An erasable unit may consist of only one erasable block. Alternatively, an erasable unit may consist of a plurality of erasable blocks; conveniently, a binary multiple of erasable blocks.
It will be understood that an erasable block will typically be much larger than a cell.
Prior to or during connection to the host, the memory locations in each cell are tested and if a defect is present in even one location in a cell, then the controller identifies the entire cell as being unusable, otherwise the entire cell is identified as being usable for storing data structures.
It will be understood that the term memory location can refer to a single bit of memory storage; whereas, the term cell refers to a large plurality of bits of memory storage, typically a cell may store 256 bytes or 512 bytes.
It will be understood that locations that can be written to individually may be formed by a plurality of physical memory locations, for example, a row of physical memory, so that in this case an entire row is the smallest unit of memory that can be written to individually.
The non-volatile memory may comprise a plurality of memory devices, or only a single memory device. The controller is, preferably, in the form of a master controller having a sub-controller incorporated into the or each memory device. Alternatively, the controller is in the form of a single controller which controls the or each memory device.
Preferably, the controller designates at least one of the usable cells in each erasable unit as being reserved whereby there are unusable cells containing defects, reserved cells for storing control information, and usable cells for storing data received from the host.
Preferably, the reserved cells are used for storing address conversion information for converting an address from the host to an address suitable for accessing the memory.
Preferably, the address conversion is effected by having a plurality of reserved cells linked together.
Preferably, each reserved cell is used to store pointer information for pointing to the next reserved cell until the last reserved cell is reached, which points to an address in the memory storing the address suitable for accessing the memory.
Preferably, reserved cells are configured to have a plurality of entries, where each entry stores a plurality of fields, whereby a field stored in one entry is used to point to a field stored in another entry and only the most recently written field stored in an entry is considered to be valid.
According to a second aspect of the present invention there is provided a controller for use with a non-volatile memory having locations that can be written to individually but can only be erased in blocks of locations, where, in use, the controller forms at least one erasable unit, where each erasable unit comprises at least one erasable block, and the controller subdivides each erasable unit into cells and reads data structures from and writes data structures to the cells on a per cell basis.
The term data structure is used to include all data stored in the memory. Thus, the term data structures includes read/write blocks (that is, blocks of data which are transferred between a PC and the memory) and also control information (that is, information which is generated by, for example, the memory controller).
According to a third aspect of the present invention there is provided a non-volatile memory for use with a controller, the memory having locations that can be written to individually but can only be erased in blocks of locations, the non-volatile memory being configured so that at least one erasable unit is formed, where each erasable unit comprises at least one erasable block, and each erasable unit is subdivided into groups of memory locations called cells, so that data structures are written to and read from the cells by the controller on a per cell basis.
The non-volatile memory may be configured by having each cell in each erasable unit tested and the results of the test for each unit written to a set of locations forming a header within that unit, so that each unit has a header containing header information.
Alternatively, in an erasable unit comprising a plurality of blocks, each cell in each erasable block may be tested and the results of the test for each erasable block written to a header within that block. The controller may read the header information from each of a plurality of erasable blocks and concatenate the header information and store the concatenated header information in a single header in an erasable unit comprising the plurality of blocks which were read.
Preferably, at least one cell in each erasable unit is designated as being reserved for storing control information.
Preferably, a plurality of reserved (control) cells are linked together to form a hierarchy of cells for effecting address conversion, and different levels in the hierarchy of cells are addressed by different bits from a logical address supplied by a host, so that the lowest cell in the hierarchy provides either the actual physical address required or pointer information for pointing to another hierarchy of cells.